The present invention relates to a semiconductor memory device.
The memory capacity of a semiconductor memory device has been recently increasing at a rate of four times every 2 to 3 years, and this trend is expected to continue in the future. This trend can be generally applied to all semiconductor memory devices irrespective of type, e.g., whether it is a random access memory or a read-only memory, or a dynamic memory or a static memory. As the memory capacity of the semiconductor memory device has increased, several problems have arisen. For instance, there is the problem of the increase in consumed current and particularly instantaneous peak current during operation. The increase in the instantaneous peak current results in the incrase of high frequency variation of a voltage component of a power source voltage. Consequently, a voltage noise is produced due to an induced voltage or the like in an input signal line and a signal line wired in a memory chip. In this respect, the operating margin of the memory circuit is limited, and various complicated circuits are accordingly required in actual use. Particularly in a dynamic memory or a static memory having an internal circuit operated in substantially a dynamic mode, charging and discharging currents flow through a number of signal lines, including essential signal lines. As a result, most signal lines are set to the initial state. Since the stray capacitance associated with the essential signal lines will generally increase as the memory capacity is increased, the charging and discharging currents flowing at the time of setting the initial states also increase. Further, in order to attain a higher operating speed of the memory device, the charging and discharging operations for the stray capacitance are carried out at a higher speed. Thus, the charging and discharging current characteristics become more abrupt.
FIG. 1 shows a conventional semiconductor memory device which has memory cells MC-11 to MC-MN arranged in a matrix array. Those of memory cells MC-11 to MC-MN disposed in the same row are commonly connected to a corresponding one of word lines W1 to WN. For example, the memory cells MC-12 to MC-M2 are connected to the word line W2. Those of the memory cells MC-11 to MC-MN arranged in the same column are commonly connected to a corresponding one of pairs of bit lines B0-1 and B1-1, B0-2 and B1-2, . . . , and B0-M and B1-M. The memory cells MC-21 and MC-2N are connected, for example, to the bit lines B0-2 and B1-2. The ends of the bit lines B0-1 to B0-M are respectively connected through MOS transistors TR01 to TR0M to a power source terminal VD, and the ends of the bit lines B1-1 to B1-M are respectively connected through the MOS transistor TR11 to TR1M to the power source terminal VD. The gates of the MOS transistors TR01 to TR0M and TR11 to TR1M are all connected to a precharge control circuit 2, and thus the MOS transistors TR01 to TR0M cooperate with the MOS transistors TR11 to TR1M to form precharge circuits PC-1 to PC-M, respectively. The word lines W1 to WN are connected to the row decoder circuit 4, and a row selection signal from the row decoder circuit 4 is selectively supplied to memory cells.
Moreover, sense amplifiers SA-1 to SA-M are respectively connected between the bit lines B0-1 and B1-1, B0-2 and B1-2, . . . , and B0-M and B1-M. An activation control circuit 6 is connectd to these sense amplifiers SA-1 to SA-M, and the sense amplifiers SA-1 to SA-M are substantially simultaneously energized by the activation signal from the activation control circuit 6, thereby amplifying data signals on the corresponding bit lines.
FIG. 2 shows a circuit diagram of the memory cell MC-11 shown in FIG. 1. The other memory cells are composed similarly to the memory cell MC-11 shown in FIG. 2. This memory cell MC-11 has load MOS transistors 10 and 11 as well as driving MOS transistors 12 and 13 connected to form a flip-flop. Transfer MOS transistors 14 and 15 are each connected between one of the bistable output terminals of the flip-flop and one of the bit lines B0-1 and B1-1. The gates of these MOS transistors 14 and 15 are connected to a word line W1.
FIG. 3 shows a circuit diagram of the sense amplifier SA-1 shown in FIG. 1. The other sense amplifiers SA-2 to SA-M are formed similarly to the sense amplifier SA-1. This sense amplifier SA-1 has load MOS transistors 20 and 21 as well as driving MOS transistors 22 and 23 connected to form a flip-flop, and an MOS transistor connected between a power source terminal VS and the driving MOS transistors 22 and 23. The gate of this MOS transistor 24 is connected to the activation control circuit 6.
In a conventional memory device as shown in FIGS. 1 through 3, the occupying area of the memory cells becomes very large with respect to the entire chip. The area of the chip depends mostly upon the size of the memory cells. Therefore, it is necessary to minimize the size of the respective memory cells as well as to form word lines of polycrystalline silicon, which is also used to form the gates of the MOS transistors 10 to 15 of the memory cells, and to arrange them rectilinearly. However, in this case, a stray capacitance is produced in a word line in a distributed-constant manner, with the result that a row selection signal on the word line W1 from the row decoder 4 is, for example, applied as an effective signal to the memory cell MS-M1 after a predetermined delay from the application of the signal to the memory cell MC-11. As the distance between the memory cells MC-11 and MC-MN is increased, the delay is accordingly lengthened.
In a case where a precharge control signal from the precharge control circuit 2 falls to a low level, as shown in FIG. 4A, the transistors TR01 to TR0M and TR11 to TR1M are rendered conductive. The bit lines B0-1 to B0-M and B1-1 to B1-M are resultantly connected through these transistors to the power source terminal VD. As a consequence, the potential of these bit lines is raised up to the VD level as shown in FIG. 4B. In this case, the precharge currents will simultaneously flow through the power source terminal VD to all the bit lines B0-1 to BO-M and B1-1 to B1-M. That is, the total of these precharge currents will instantaneously flow, as shown in FIG. 4C, through the power line (not shown) connecting the power source (not shown) to the power source terminal VD. The row selection signal is generated from the row detector circuit 4 as shown in FIG. 4D, after the bit llines B0-1 to B0-M and B1-1 to B1-M are precharged up to the predetermined voltage level in this manner. As shown in FIG. 4E, this row selection signal is applied to the memory cell disposed on the row located the most distant from the row decoder circuit 4 after the predetermined time is elapsed.
Since all the bit lines are simultaneously precharged to the predetermined voltage level in the memory device shown in FIG. 1, as described above, when the precharging operation starts, a peak current having a high instantaneous value will flow through the current line connected to the power source terminal VD. Thus, a noise voltage is induced to the input signal line, etc., as described above, thereby effecting an adverse influence to the operation of the conventoinal memory device.
Since a discharging current will flow through the MOS transistor 24 and the corresponding MOS transistors of the other sense amplifiers SA-2 to SA-M when the sense amplifiers SA-1 to SA-M are energized simultaneously, a large peak current will flow through the power line (not shown) connected to the power source terminal VS. Thus, the same problem as described above will occur.